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? semiconductor components industries, llc, 2000 august, 2000 rev. 0 1 publication order number: 74vcxh16240/d 74vcxh16240 low-voltage 1.8/2.5/3.3v 16-bit buffer with 3.6 vtolerant inputs and outputs (3state, inverting) the 74vcxh16240 is an advanced performance, inverting 16bit buffer. it is designed for very highspeed, very lowpower operation in 1.8 v, 2.5 v or 3.3 v systems. when operating at 2.5 v (or 1.8 v) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 v busses. it is guaranteed to be overvoltage tolerant to 3.6 v. the 74vcxh16240 is nibble controlled with each nibble functioning identically, but independently. the control pins may be tied together to obtain full 16bit operation. the 3state outputs are controlled by an output enable (oen ) input for each nibble. when oen is low, the outputs are on. when oen is high, the outputs are in the high impedance state. the data inputs include active bushold circuitry, eliminating the need for external pullup resistors to hold unused or floating inputs at a valid logic state. ? designed for low voltage operation: v cc = 1.653.6 v ? 3.6 v tolerant inputs and outputs ? high speed operation: 2.5 ns max for 3.0 to 3.6 v 3.0 ns max for 2.3 to 2.7 v 6.0 ns max for 1.65 to 1.95 v ? static drive: 24 ma drive at 3.0 v 18 ma drive at 2.3 v 6 ma drive at 1.65 v ? supports live insertion and withdrawal ? includes active bushold to hold unused or floating inputs at a valid logic state ? i off specification guarantees high impedance when v cc = 0 v 2 ? near zero static supply current in all three logic states (20 m a) substantially reduces system power requirements ? latchup performance exceeds 300ma @ 125 c ? esd performance: human body model >2000 v; machine model >200 v 2note: to ensure the outputs activate in the 3state condition, the output enable pins should be connected to v cc through a pullup resistor. the value of the resistor is determined by the current sinking capability of the output connected to the oe pin. http://onsemi.com marking diagram a = assembly location wl = wafer lot yy = year ww = work week tssop48 dt suffix case 1201 1 48 74vcxh16240dt awlyyww 1 48 device package shipping ordering information 74vcxh16240dt tssop 39 / rail 74vcxh16240dtr tssop 2500 / reel
74vcxh16240 http://onsemi.com 2 48 1 oe2 oe1 47 2 d0 o0 46 3 d1 o1 45 4 gnd gnd 44 5 d2 o2 43 6d3 o3 42 7 v cc v cc 41 8 d4 o4 40 9 d5 o5 39 10 gnd gnd 38 11 d6 o6 37 12 d7 o7 36 13 d8 o8 35 14 d9 o9 34 15 gnd gnd 33 16 d10 o10 32 17 d11 o11 31 18 v cc v cc 30 19 d12 o12 29 20 d13 o13 28 21 gnd gnd 27 22 d14 o14 26 23 d15 o15 25 24 oe3 oe4 oe1 oe2 d0:3 d4:7 o0:3 o4:7 oe3 oe4 d8:11 d12:15 o8:11 o12:15 one of four 1 48 25 24 figure 1. 48lead pinout (top view) figure 2. logic diagram 1 48 25 24 d0 47 d1 46 d2 44 d3 43 o0 2 en1 oe1 oe2 oe3 oe4 o1 3 o2 5 o3 6 en2 en3 en4 d4 41 d5 40 d6 38 d7 37 o4 8 o5 9 o6 11 o7 12 d8 36 d9 35 d10 33 d11 32 o8 13 o9 14 o10 16 o11 17 d12 30 d13 29 d14 27 d15 26 o12 19 o13 20 o14 22 o15 23 1 ? 2 ? 3 ? 4 ? 1 1 1 1 pin names function output enable inputs inputs outputs pins oen d0d15 o0o15 oe1 d0:3 o0:3 oe2 d4:7 o4:7 oe3 d8:11 o8:11 oe4 d12:15 o12:15 l l h l l h l l h l l h l h l l h l l h l l h l h x z h x z h x z h x z h = high voltage level; l = low voltage level; z = high impedance state; x = high or low voltage level and transitions are acce ptable, for i cc reasons, do not float inputs
74vcxh16240 http://onsemi.com 3 absolute maximum ratings* symbol parameter value condition unit v cc dc supply voltage 0.5 to +4.6 v v i dc input voltage 0.5 v i +4.6 v v o dc output voltage 0.5 v o +4.6 output in 3state v 0.5 v o v cc + 0.5 note 1.; outputs active v i ik dc input diode current 50 v i < gnd ma i ok dc output diode current 50 v o < gnd ma +50 v o > v cc ma i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range 65 to +150 c * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated co nditions is not implied. 1. i o absolute maximum rating must be observed. recommended operating conditions symbol parameter min typ max unit v cc supply voltage operating data retention only 1.65 1.2 3.3 3.3 3.6 3.6 v v i input voltage 0.3 3.6 v v o output voltage (active state) (3state) 0 0 v cc 3.6 v i oh high level output current, v cc = 3.0v 3.6v 24 ma i ol low level output current, v cc = 3.0v 3.6v 24 ma i oh high level output current, v cc = 2.3v 2.7v 18 ma i ol low level output current, v cc = 2.3v 2.7v 18 ma i oh high level output current, v cc = 1.65 1.95v 6 ma i ol low level output current, v cc = 1.65 1.95v 6 ma t a operating freeair temperature 40 +85 c d t/ d v input transition rise or fall rate, v in from 0.8v to 2.0v, v cc = 3.0v 0 10 ns/v
74vcxh16240 http://onsemi.com 4 dc electrical characteristics t a = 40 c to +85 c symbol characteristic condition min max unit v ih high level input voltage (note 2.) 1.65v v cc < 2.3v 0.65 x v cc v 2.3v v cc 2.7v 1.6 2.7v < v cc 3.6v 2.0 v il low level input voltage (note 2.) 1.65v v cc < 2.3v 0.35 x v cc v 2.3v v cc 2.7v 0.7 2.7v < v cc 3.6v 0.8 v oh high level output voltage 1.65v v cc 3.6v; i oh = 100 m a v cc 0.2 v v cc = 1.65v; i oh = 6ma 1.25 v cc = 2.3v; i oh = 6ma 2.0 v cc = 2.3v; i oh = 12ma 1.8 v cc = 2.3v; i oh = 18ma 1.7 v cc = 2.7v; i oh = 12ma 2.2 v cc = 3.0v; i oh = 18ma 2.4 v cc = 3.0v; i oh = 24ma 2.2 v ol low level output voltage 1.65v v cc 3.6v; i ol = 100 m a 0.2 v v cc = 1.65v; i ol = 6ma 0.3 v cc = 2.3v; i ol = 12ma 0.4 v cc = 2.3v; i ol = 18ma 0.6 v cc = 2.7v; i ol = 12ma 0.4 v cc = 3.0v; i ol = 18ma 0.4 v cc = 3.0v; i ol = 24ma 0.55 i i input leakage current 1.65v v cc 3.6v; 0v v i 3.6v 5.0 m a i i(hold) minimum bushold input current v cc = 3.0v, v in = 0.8v 75 m a () v cc = 3.0v, v in = 2.0v 75 v cc = 2.3v, v in = 0.7v 45 v cc = 2.3v, v in = 1.6v 45 v cc = 1.65v, v in = 0.57v 25 v cc = 1.65v, v in = 1.07v 25 i i (od) minimum bushold overdrive c t n d d t ch st t v cc = 3.6v, (note 3.) 450 m a () current needed to change state v cc = 3.6v, (note 4.) 450 v cc = 2.7v, (note 3.) 300 v cc = 2.7v, (note 4.) 300 v cc = 1.95v, (note 3.) 200 v cc = 1.95v, (note 4.) 200 i oz 3state output current 1.65v v cc 3.6v; 0v v o 3.6v; v i = v ih or v il 10 m a i off poweroff leakage current v cc = 0v; v i or v o = 3.6v 10 m a i cc quiescent supply current (note 5.) 1.65v v cc 3.6v; v i = gnd or v cc 20 m a 1.65v v cc 3.6v; 3.6v v i , v o 3.6v 20 m a d i cc increase in i cc per input 2.7v < v cc 3.6v; v ih = v cc 0.6v 750 m a 2. these values of v i are used to test dc electrical characteristics only. 3. an external driver must source at least the specified current to switch from lowtohigh 4. an external driver must source at least the specified current to switch from hightolow 5. outputs disabled or 3state only.
74vcxh16240 http://onsemi.com 5 ac characteristics (note 6.; t r = t f = 2.0ns; c l = 30pf; r l = 500 w ) limits t a = 40 c to +85 c v cc = 3.0v to 3.6v v cc = 2.3v to 2.7v v cc = 1.65 to 1.95v symbol parameter waveform min max min max min max unit t plh t phl propagation delay input to output 1 0.8 0.8 2.5 2.5 1.0 1.0 3.0 3.0 1.5 1.5 6.0 6.0 ns t pzh t pzl output enable time to high and low level 2 0.8 0.8 3.5 3.5 1.0 1.0 4.1 4.1 1.5 1.5 8.2 8.2 ns t phz t plz output disable time from high and low level 2 0.8 0.8 3.5 3.5 1.0 1.0 3.8 3.8 1.5 1.5 7.8 7.8 ns t oshl t oslh outputtooutput skew (note 7.) 0.5 0.5 0.5 0.5 0.75 0.75 ns 6. for c l = 50pf, add approximately 300ps to the ac maximum specification. 7. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same d evice. the specification applies to any outputs switching in the same direction, either hightolow (t oshl ) or lowtohigh (t oslh ); parameter guaranteed by design. dynamic switching characteristics t a = +25 c symbol characteristic condition typ unit v olp dynamic low peak voltage v cc = 1.8v, c l = 30pf, v ih = v cc , v il = 0v 0.25 v (note 8.) v cc = 2.5v, c l = 30pf, v ih = v cc , v il = 0v 0.6 v cc = 3.3v, c l = 30pf, v ih = v cc , v il = 0v 0.8 v olv dynamic low valley voltage v cc = 1.8v, c l = 30pf, v ih = v cc , v il = 0v 0.25 v (note 8.) v cc = 2.5v, c l = 30pf, v ih = v cc , v il = 0v 0.6 v cc = 3.3v, c l = 30pf, v ih = v cc , v il = 0v 0.8 v ohv dynamic high valley voltage v cc = 1.8v, c l = 30pf, v ih = v cc , v il = 0v 1.5 v (note 9.) v cc = 2.5v, c l = 30pf, v ih = v cc , v il = 0v 1.9 v cc = 3.3v, c l = 30pf, v ih = v cc , v il = 0v 2.2 8. number of outputs defined as ano. measured with an1o outputs switching from hightolow or lowtohigh. the remaining output is measured in the low state. 9. number of outputs defined as ano. measured with an1o outputs switching from hightolow or lowtohigh. the remaining output is measured in the high state. capacitive characteristics symbol parameter condition typical unit c in input capacitance note 10. 6 pf c out output capacitance note 10. 7 pf c pd power dissipation capacitance note 10., 10mhz 20 pf 10. v cc = 1.8, 2.5 or 3.3v; v i = 0v or v cc .
74vcxh16240 http://onsemi.com 6 waveform 1 - propagation delays t r = t f = 2.0ns, 10% to 90%; f = 1mhz; t w = 500ns v ih 0v v oh v ol dn on t phl t plh waveform 2 - output enable and disable times t r = t f = 2.0ns, 10% to 90%; f = 1mhz; t w = 500ns v ih 0v 0v oen on t pzh v cc t phz t pzl t plz on v m v m v m v m v m v m figure 3. ac waveforms v m v oh v y v x v ol v cc symbol 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v v ih 2.7v v cc v cc v m 1.5v v cc /2 v cc /2 v x v ol + 0.3v v ol + 0.15v v ol + 0.15v v y v oh 0.3v v oh 0.15v v oh 0.15v open pulse generator r t dut v cc r l r l c l 6v or v cc 2 gnd test switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v; v cc 2 at v cc = 2.5 0.2v; 1.8 0.15v t pzh , t phz gnd c l = 30pf or equivalent (includes jig and probe capacitance) r l = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) figure 4. test circuit
74vcxh16240 http://onsemi.com 7 waveform 3 - propagation delays t r = t f = 2.0ns, 10% to 90%; f = 1mhz; t w = 500ns v ih 0v v oh v ol dn on t phl t plh waveform 4 - output enable and disable times t r = t f = 2.0ns, 10% to 90%; f = 1mhz; t w = 500ns v ih 0v 0v oen on t pzh v cc t phz t pzl t plz on v m v m v m v m v m v m figure 5. ac waveforms v m v oh v y v x v ol v cc symbol 3.3v 0.3v 2.7v v ih 2.7v 2.7v v m 1.5v 1.5v v x v ol + 0.3v v ol + 0.3v v y v oh 0.3v v oh 0.3v open pulse generator r t dut v cc r l r l c l 6v or v cc 2 gnd test switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v; v cc 2 at v cc = 2.5 0.2v; 1.8 0.15v t pzh , t phz gnd c l = 50pf or equivalent (includes jig and probe capacitance) r l = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) figure 6. test circuit
74vcxh16240 http://onsemi.com 8 ac characteristics (t r = t f = 2.0ns; c l = 50pf; r l = 500 w ) limits t a = 40 c to +85 c v cc = 3.0v to 3.6v v cc = 2.7v symbol parameter waveform min max min max unit t plh t phl propagation delay input to output 3 1.0 1.0 3.9 3.9 5.3 5.3 ns t pzh t pzl output enable time to high and low level 4 1.0 1.0 5.0 5.0 6.1 6.1 ns t phz t plz output disable time from high and low level 4 1.0 1.0 4.4 4.4 4.8 4.8 ns t oshl t oslh outputtooutput skew (note 11.) 0.5 0.5 0.5 0.5 ns 11. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same d evice. the specification applies to any outputs switching in the same direction, either hightolow (t oshl ) or lowtohigh (t oslh ); parameter guaranteed by design.
74vcxh16240 http://onsemi.com 9 figure 7. carrier tape specifications d 1 for components 10 pitches cumulative tolerance on tape 0.2 mm ( 0.008") 2.0 mm 1.2 mm and larger center lines of cavity embossment user direction of feed k 0 see note 2 p 0 p 2 d e f w b 0 + + + k t b 1 top cover tape p see note 2 a 0 for machine reference only including draft and radii concentric around b 0 r min. tape and components shall pass around radius r" without damage bending radius *top cover tape thickness (t 1 ) 0.10 mm (0.004") max. embossed carrier embossment typical component cavity center line typical component center line maximum component rotation 10 camber (top view) allowable camber to be 1 mm/100 mm nonaccumulative over 250 mm 100 mm (3.937") 1 mm (0.039") max 250 mm (9.843") 1 mm max tape embossed carrier dimensions (see notes 1 and 2) tape size b 1 max d d 1 e f k p p 0 p 2 r t w 24mm 20.1mm (0.791") 1.5 + 0.1mm -0.0 (0.059 +0.004" -0.0) 1.5mm min (0.060") 1.75 0.1 mm (0.069 0.004") 11.5 0.10 mm (0.453 0.004") 11.9 mm max (0.468") 16.0 0.1 mm (0.63 0.004") 4.0 0.1 mm (0.157 0.004") 2.0 0.1 mm (0.079 0.004") 30 mm (1.18") 0.6 mm (0.024") 24.3 mm (0.957") 1. metric dimensions governenglish are in parentheses for reference only. 2. a 0 , b 0 , and k 0 are determined by component size. the clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. the component cannot rotate more than 10 within the determined cavity
74vcxh16240 http://onsemi.com 10 figure 8. reel dimensions 13.0 mm 0.2 mm (0.512" 0.008") 1.5 mm min (0.06") 50 mm min (1.969") 20.2 mm min (0.795") full radius t max g a reel dimensions tape size a max g t max 24 mm 360 mm (14.173") 24.4 mm + 2.0 mm, -0.0 (0.961" + 0.078", -0.00) 30.4 mm (1.197") figure 9. reel winding direction direction of feed barcode label hole pocket
74vcxh16240 http://onsemi.com 11 tape trailer (connected to reel hub) no components 160 mm min tape leader no components 400 mm min components direction of feed cavity tape top tape figure 10. tape ends for finished goods figure 11. reel configuration user direction of feed l package footprint f k g 48 leads
74vcxh16240 http://onsemi.com 12 package dimensions tssop dt suffix case 120101 issue a ??? ??? ??? s u m 0.12 (0.005) v s t s u m 0.254 (0.010) t v b a l k u 48x ref pin 1 ident. 124 25 48 0.076 (0.003) seating d t plane dim min max min max inches millimeters a 12.40 12.60 0.488 0.496 b 6.00 6.20 0.236 0.244 c --- 1.10 --- 0.043 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.50 bsc 0.0197 bsc h 0.37 --- 0.015 --- j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.17 0.27 0.007 0.011 k1 0.17 0.23 0.007 0.009 l 7.95 8.25 0.313 0.325 m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 5. terminal numbers are shown for reference only. 6. dimensions a and b are to be determined at datum plane -w-. c g h w detail e j k1 k j1 section nn m 0.25 (0.010) f detail e n n on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. 74vcxh16240/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk

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